High-performance processor design based on 3D on-chip cache
| Autor: | Xie Chengmin, Guangbao Shan, Lei Yi, Song Liu |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Computer Networks and Communications
Cache coloring Computer science Pipeline burst cache 02 engineering and technology Cache-oblivious algorithm Cache pollution 01 natural sciences Artificial Intelligence Write-once Cache invalidation 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Cache algorithms 010302 applied physics business.industry 020202 computer hardware & architecture Microarchitecture Smart Cache Hardware and Architecture Embedded system Computer data storage Page cache Cache business Software Access time |
| Zdroj: | Microprocessors and Microsystems. 47:486-490 |
| ISSN: | 0141-9331 |
| DOI: | 10.1016/j.micpro.2016.07.009 |
| Popis: | We implement a high-performance processor architecture based 3D on-chip cache, Using 3D integration technology.We simulate the performance of the 3D processor and 3D cache at different node, using 3D Cacti tools and theoretical algorithms.The performance of the 3D processor and 3D cache is obviously improved, including power consumption of the storage system, access time and cycle time of the processor, and critical paths delay. Interconnection becomes one of main concerns in current and future microprocessor designs from both performance and consumption. Three-dimensional integration technology, with its capability to shorten the wire length, is a promising method to mitigate the interconnection related issues. In this paper we implement a novel high-performance processor architecture based 3D on-chip cache to show the potential performance and power benefits achievable through 3D integration technology. We separate other logic module and cache module and stack 3D cache with the processor which reduces the global interconnection, power consumption and improves access speed. The performance of 3D processor and 3D cache at different node is simulated using 3D Cacti tools and theoretical algorithms. The results show that comparing with 2D, power consumption of the storage system is reduced by about 50%, access time and cycle time of the processor increase 18.57% and 21.41%, respectively. The reduced percentage of the critical path delay is up to 81.17%. |
| Databáze: | OpenAIRE |
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