State reduction for efficient digital calibration of analog/RF integrated circuits
| Autor: | Angela Arapoyanni, John Liaperdos, Yiorgos Tsiatouhas |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering Overhead (engineering) Electrical engineering 02 engineering and technology Integrated circuit Chip 020202 computer hardware & architecture Surfaces Coatings and Films law.invention Reduction (complexity) CMOS Hardware and Architecture law Signal Processing 0202 electrical engineering electronic engineering information engineering Performance prediction Electronic engineering Calibration business Frequency mixer |
| Zdroj: | Analog Integrated Circuits and Signal Processing. 90:65-79 |
| ISSN: | 1573-1979 0925-1030 |
| Popis: | Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration techniques have been developed that are applied to fabricated chips, aiming at the restoration of a circuit's performance to its acceptable range of values that are defined by the specifications. To allow calibration, adjustable elements are introduced that provide multiple states of a circuit's operation through built-in tuning knobs. Digital calibration--that refers to the case of discrete tuning knob settings--is performed by switching to a circuit's state at which all performance characteristics are restored to their specified ranges. Due to the large number of performance characteristics of interest a large space of tuning knob settings should be explored, that leads to a series of practical considerations that need to be addressed, such as increased times required for calibration preparation and conduction, or chip area overhead if built-in tuning knobs are used. In this paper we present a method to maintain a desired level of yield recovery through the exploitation of only a minimum number of calibration states, also ensuring low cost by shortening calibration times and reducing chip area overhead. The proposed method is assessed through case studies conducted on a typical RF mixer designed in a 180 nm CMOS technology. |
| Databáze: | OpenAIRE |
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