8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz
| Autor: | Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim, Jin-hyeok Choi |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Record locking
business.industry Computer science 020208 electrical & electronic engineering Process (computing) Linearity 020207 software engineering 02 engineering and technology Phase-locked loop Embedded system Phase noise 0202 electrical engineering electronic engineering information engineering Key (cryptography) Digitally controlled oscillator business Block (data storage) |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2017.7870307 |
| Popis: | There continue to be efforts to develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several approaches for fully synthesized digital PLLs [1–4] via gate-level implementation of a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC). Though automated layout has been achieved, the lock-range and phase-noise performance are subject to process variations. Critical performance-limiting blocks, such as the TDC and DCO, should be carefully designed with analog circuit simulators, diluting the inherent benefits of digital design. This work presents a highly programmable and synthesizable TDC- and DCO-less fractional-N PLL architecture, employing a phase-locked direct-digital synthesizer (PLDDS) driven by a free-running oscillator. The PLDDS design is specified entirely in a register-transfer level (RTL) hardware-description language (HDL) without any need for analog simulation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|