Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology
| Autor: | Shen-Fu Hsiao, Chua-Chin Wang, Chuan-Lin Wu, Sheng-Hun Chen |
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| Rok vydání: | 2003 |
| Předmět: |
Correctness
business.industry Computer science Integrated circuit design Set (abstract data type) CMOS Parallel processing (DSP implementation) Computer architecture Embedded system Code (cryptography) Verilog Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer AND gate Hardware_LOGICDESIGN computer.programming_language |
| Zdroj: | ICECS |
| DOI: | 10.1109/icecs.1999.814388 |
| Popis: | In this paper, we present designs of a set of four non-homogeneous ALUs which can be employed in the next generation 64-bit /spl times/86-compatible microprocessors. The entire design is realized by synthesizable Verilog RTL (register-transfer level) code. The gate level code is generated by Synopsys using COMPASS 0.6 um 1P3M cell library, and UMC 0.25 um 1P5M cell library. The correctness of the functionality of the individual ALU is verified in both RTL code and gate level code after the synthesization. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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