Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

Autor:	Joo-Won Lee, Myung-Hwan Oh, Ja-hum Ku, Kang-soo Chu, Nae-In Lee, Jong-Ho Yang, Ho-Kyu Kang, Jun-Ha Lee, Jae-Eun Park, Hee-Sung Kang, Kwang-Pyuk Suh, Moon-han Park
Rok vydání:	2004
Předmět:	Materials science business.industry Electrical engineering Short-channel effect PMOS logic Threshold voltage chemistry.chemical_compound Atomic layer deposition chemistry Gate oxide Etching (microfabrication) MOSFET Silicide Optoelectronics business
Zdroj:	2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
Popis:	For the first time, by employing low thermal budget processes of ALD SiO/sub 2/ and ALD SiN as gate spacer and silicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO/sub 2/ and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiC/sub 2/SiN processes are comparable to those with conventional high temperature CVD SiO/sub 2//SiN processes. In conclusion, ALD SiO/sub 2/ and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90 nm CMOSFETs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::fa742533006859e5e221246ad493a9cd https://doi.org/10.1109/vlsit.2003.1221083 Zobrazit plný text záznamu