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In this paper, a new synthesis system, called TASS (TAbu search Synthesis System), is presented. It enables a Register-Transfer Level (RTL) implementation from a functional VHDL description. Furthermore, an emphasis on how testability evaluation is incorporated in the synthesis process in order to generate not only optimized designs, with regard to area and delay, but also fully and easily testable architectures. Such testability evaluation is performed at the RTL using developed testability measures. These measures are benchmarked on high-level synthesized examples and the testability analysis of the generated designs is performed using the test compiler tool of Synopsys. |
