Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs
| Autor: | Martin Christopher Holland, Z. Q. Wu, Aryan Afzalian, E. Chen, T. Vasen, Blandine Duriez, M.J.H. van Dal, Gerben Doornbos, Tzer-Min Shen, Carlos H. Diaz, Tung-Tsun Chen, Georgios Vellianitis, S.-K Su |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Very-large-scale integration Materials science business.industry Gate stack Nanowire 02 engineering and technology Dielectric 021001 nanoscience & nanotechnology 01 natural sciences Atomic layer deposition Stack (abstract data type) CMOS Electrical resistivity and conductivity 0103 physical sciences Optoelectronics 0210 nano-technology business |
| Zdroj: | 2018 IEEE International Electron Devices Meeting (IEDM). |
| Popis: | We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform. |
| Databáze: | OpenAIRE |
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