Architecture and modeling of a parallel digital processor based image processing system

Autor:	Shirish P. Kshirsagar, David Andrew Hartley
Rok vydání:	1994
Předmět:	Digital signal processor business.industry Computer science Message passing Image processing Petri net Shared memory Media processor Embedded system Digital image processing Computer data storage business Digital signal processing Computer hardware
Zdroj:	Visual Communications and Image Processing '94.
ISSN:	0277-786X
DOI:	10.1117/12.185937
Popis:	The paper describes an image processing system which uses both shared memory and message passing. Shared memory is used in conjunction with a high speed parallel bus to transfer image data; message passing is used for general inter-processor communication. A prototype system based upon the Texas Instruments TMS320C40 digital signal processor is currently in the final stages of construction. A Petri Net model of the communication aspects of the TMS320C40 processor has been developed. Features of the Petri Net software are discussed and the raw communication performance of the TMS320C40 shown. The modeling of a four and sixteen processor system applied to 2D FFT transforms is described.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::fa1c8576beb3cbb44594dc6bcccbcdf1 https://doi.org/10.1117/12.185937 Zobrazit plný text záznamu