| Autor: |
Seouk-Kyu Choi, Young-Kwan Kim, Seung-Jun Bae, Seung-Hyun Cho, Jae-Woo Jung, Dae Hyun Kim, Byung-Cheol Kim, Sung-Woo Yoon, Jae-Koo Park, Yong-Hun Kim, Si-Hyeong Cho, Jung-Bae Lee, Jinyong Choi, Dae-Hyun Kwon, Seong-hoon Kim, Chan-Young Kim, Byongwook Na, Yong-Jun Kim, Jae-Woo Lee, Dong-Yeon Park, Hye-In Choi, Reum Oh, Hyung-Jin Kim, Min-Su Ahn, Dongkeon Lee, Jihwa You, Nam Sung Kim, Jaemin Choi, Jun-Ho Kim, Jeong-Don Ihm, Hyung-Seok Cha, Kyoung-Ho Kim, Young-Jae Park, Min-Soo Jang |
| Rok vydání: |
2021 |
| Předmět: |
|
| Zdroj: |
ISSCC |
| DOI: |
10.1109/isscc42613.2021.9366050 |
| Popis: |
The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
