| Autor: |
Carl D. Dietz, Tim Fischer, James Vinh, Samuel D. Naffziger, Kevin A. Hurd, Kathryn Wilcox, Dave Johnson, Jonathan White, Scott A. Hilker, Aaron Horiuchi, Srikanth Arekapudi, Golden Michael L, Hugh McIntyre, Eric W. Busta |
| Rok vydání: |
2011 |
| Předmět: |
|
| Zdroj: |
ISSCC |
| DOI: |
10.1109/isscc.2011.5746227 |
| Popis: |
AMD's 2-core “Bulldozer” module contains 213 million transistors in an 11-metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture [1] improves performance and frequency while reducing area and power compared to a previous AMD x86–64 CPU in the same process [2]. To achieve these goals, the design reduced the number of FO4 inverter delays/cycle by more than 20%, achieving higher frequencies in the same power envelope even with increased core counts. The 2-core CPU module area (including 2MB L2 cache) is 30.9mm2 (Fig. 4.5.7). |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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