A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS
| Autor: | Doyoon Kim, Jungsoo Kim, Junghwan Yoo, Jae-Sung Rieh, Kiryong Song |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Frequency synthesizer
Radiation Materials science business.industry 020208 electrical & electronic engineering dBc 020206 networking & telecommunications 02 engineering and technology Frequency divider Phase-locked loop CMOS Phase noise 0202 electrical engineering electronic engineering information engineering Charge pump Optoelectronics Electrical and Electronic Engineering business Phase frequency detector |
| Zdroj: | IEEE Transactions on Terahertz Science and Technology. 8:784-792 |
| ISSN: | 2156-3446 2156-342X |
| DOI: | 10.1109/tthz.2018.2875796 |
| Popis: | A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3–283.7 GHz and a phase noise of −53.5 dBc/Hz at 100 kHz (in band) and −78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μ m2 excluding probing pads. |
| Databáze: | OpenAIRE |
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