| Autor: |
Katsura Miyashita, Masaki Satake, Katsuyoshi Kodera, Soichi Inoue, Kazuhiro Takahata, Hideaki Harakawa, Yosuke Kitamura, Hiroharu Fujise, Shoji Mimotogi, Koutaro Sho, Tatsuya Ishida, Tatsuhiko Ema, Kenji Yoshida, Suigen Kyoh, Kazutaka Ishigo, Masafumi Asano, Hideki Kanai, Takuya Kono, Akiko Nomachi |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
Optical Microlithography XXI. |
| ISSN: |
0277-786X |
| DOI: |
10.1117/12.772201 |
| Popis: |
We have designed the lithography process for 32nm node logic devices under th e 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um 2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects. Keywords : single exposure, low-k1 lithography, 32nm-node, dose-focus budget INTRODUCTION Immersion lithography is needed to shrink the design rule. The appearance of immersion lithography extends the optical lithography. In 45nm node, over 1.0NA tool is useful for pulling up the k 1 factor. The k 1 factors of 45nm node are about 0.37 for local metal level and 0.44 for contact hole level. For 32nm node, over 1.3NA tool becomes to be available. According to the design rule shrink trend, the minimum pitch of local metal and hole is about 100nm. The k1 factor is 0.34 for critical levels. Then, we have to overcome the issues of the low-k |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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