| Autor: |
F. Miyaji, Y. Matsuyama, K. Seno, T. Emori, Y. Hagiwara, Y. Kanaishi |
| Rok vydání: |
1990 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 25:68-71 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/4.50286 |
| Popis: |
A multibit test (MBT) trigger circuit for megabit SRAM packages with no unused pins is discussed. The features of the MBT trigger circuit are a logic trigger mode without using any additional pins and practical use of counter circuits. The essence of trigger mode selection is that two pulses are for MBT set and three pulses are for MBT reset. In this way, a logic trigger mode that does not use NC pins is especially effective as a 4-Mb SRAM. In addition, the proposed scheme is able to act as a logic trigger for an MBT circuit. The scheme is simple and effective. The logic trigger mode is proposed for future standardization. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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