Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC
| Autor: | Satwik Patnaik, Mohammed Nabeel, Venkata Chaitanya Krishna Chekuri, Heechun Park, Sung Kyu Lim, Alabi Bojesomo, Johann Knechtel, Majid Ahadi Dolatsara, Jinwoo Kim, Ozgur Sinanoglu, Madhavan Swaminathan, Saibal Mukhopadhyay |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
021110 strategic
defence & security studies business.industry Computer science Design flow 0211 other engineering and technologies 02 engineering and technology Integrated circuit Industrial and Manufacturing Engineering 020202 computer hardware & architecture Electronic Optical and Magnetic Materials law.invention Network on a chip law Embedded system Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Interposer Electronic design automation Signal integrity Electrical and Electronic Engineering Routing (electronic design automation) business Power network design |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:2047-2060 |
| ISSN: | 2156-3985 2156-3950 |
| DOI: | 10.1109/tcpmt.2020.3033136 |
| Popis: | Interposer-based 2.5-D integrated circuits (ICs) enable the chip-level reuse of hard intellectual properties (IPs), also known as chiplets. Such system-level integration shortens the design cycle considerably for large-scale and heterogeneous chips. Besides traditional interposers, which only provide passive elements and routing, active interposers are furthermore comprised of logic components. When implemented carefully using a dedicated electronic design automation (EDA) flow, an active interposer can significantly improve the design quality and flexibility for 2.5-D ICs. In this article, we present a complete EDA flow and design strategies targeting, such active interposer-based 2.5-D ICs. Our key contributions include the coanalysis of power, performance, signal and power integrity, and the related co-optimization of chiplets and the active interposer. Our benchmark is a 64-core RISC-V architecture, organized into multiple chiplets and interconnected by a system-level network-on-chip (NoC). For efficiency, we embed the NoC routers and integrated voltage regulators (IVRs) into the active interposer. Moreover, we integrate security monitors into the interposer-based NoC to protect the system and its shared memories against adversarial traffic. The simple yet powerful benefit of this implementation is to offer security by construction, as it is based on a clear physical separation between critical and trusted components (the system-level NoC) versus commodity components (the chiplets). We contrast our active, secured design to a passive, unsecured design baseline of the same RISC-V benchmark and find that the active design reduces the silicon area by 18.5%, power by 3.2%, and IR drop by 73.7%. |
| Databáze: | OpenAIRE |
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