Cornerless active area cell and Bi-T-MOS process for sub-half micron SRAMs
| Autor: | Yoshio Kohno, Kazuhito Tsutsumi, H. Miyoshi, Hirotada Kuriyama, M. Ishida, T. Ipposhi |
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| Rok vydání: | 2002 |
| Předmět: |
Materials science
business.industry Transistor Bent molecular geometry Process (computing) Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Line (electrical engineering) law.invention law Thin-film transistor Memory cell Hardware_INTEGRATEDCIRCUITS Optoelectronics Common gate business Word (computer architecture) |
| Zdroj: | Proceedings of 1994 VLSI Technology Symposium. |
| DOI: | 10.1109/vlsit.1994.324434 |
| Popis: | This paper presents a novel memory cell and process technology. The memory cell adopts the symmetry layout which has cornerless active area, a single bent word line and common gate TFTs. Furthermore, this memory cell realizes large cell ratio using a direct contact off-set resistance. The proposed process technology is optimization of bipolar, TFT and CMOS process (Bi-T-MOS). The Bi-T-MOS technology decreases the poly-silicon layers to triple-level without decreasing performance of the transistors. > |
| Databáze: | OpenAIRE |
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