A low-inductance, low-I/sub c/ HTS junction process
| Autor: | M. Sergant, J. Luine, R. Hu, H. Chan, J.M. Murduck, C.L. Pettiette-Hall, J.F. Burch, S. Schwarzbek |
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| Rok vydání: | 1997 |
| Předmět: |
Josephson effect
Digital electronics Fabrication High-temperature superconductivity Materials science business.industry Condensed Matter Physics Electronic Optical and Magnetic Materials law.invention Inductance Taguchi methods law Parasitic element Optoelectronics Electrical and Electronic Engineering Resistor business |
| Zdroj: | IEEE Transactions on Appiled Superconductivity. 7:2940-2943 |
| ISSN: | 1051-8223 |
| DOI: | 10.1109/77.621923 |
| Popis: | One of the challenges In fabricating digital circuitry with high temperature superconductors (HTS) is in developing a reliable junction process. The requirements of this junction process include: low-parasitic inductance, well-targeted and reproducible total inductance, uniformity in I/sub c/ and R/sub n/, and also well-targeted I/sub c/ and I/sub c/R/sub n/ product greater than 300 /spl mu/V at 65 K. Junction inductance can be greatly reduced by fabrication above a groundplane. Yet the addition of a groundplane introduces fabrication issues such as film smoothness and maintenance of epitaxy through the multiple layers necessary. Step-edge junctions and SNS edge junctions with groundplanes are examined and compared through a Taguchi experimental design series. Process equipment modifications in our HTS foundry necessary to reach our fabrication goals are outlined. |
| Databáze: | OpenAIRE |
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