A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET
| Autor: | Morteza Fathipour, Amin Rassekh |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Materials science Dopant business.industry Transistor Monte Carlo method Silicon on insulator 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Atomic and Molecular Physics and Optics Electronic Optical and Magnetic Materials law.invention law Modeling and Simulation 0103 physical sciences Optoelectronics Work function Node (circuits) Sensitivity (control systems) Electrical and Electronic Engineering 0210 nano-technology business Nanoscopic scale |
| Zdroj: | Journal of Computational Electronics. 19:631-639 |
| ISSN: | 1572-8137 1569-8025 |
| DOI: | 10.1007/s10825-020-01475-9 |
| Popis: | We present a detailed study on the n-channel single-gate junctionless transistor (JLT) at the $${10}-\hbox{nm}$$ node. We investigate the influence of its structural parameters on the on-state current and the off-state leakage current. Furthermore, we show that the use of high-k spacers may not be advantageous in future nanoscale junctionless transistors and confirm this argument by simulation. We also present the results of our investigation on process variations, including the sensitivity of the JLT to random dopant fluctuations as well as the gate work function using Monte Carlo simulations. These results are then compared with those of a conventional FinFET. Finally, we provide design guidelines for JLTs at $${10}-\hbox{nm}$$ gate length. |
| Databáze: | OpenAIRE |
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