13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique
| Autor: | Kangwoo Park, Kwanho Kim, Cheoljoong Park, Kayoung Cho, Kun-Ok Ahn, Chankeun Kwon, Jong Woo Kim, Hyun Chul Lee, Hyunseok Song, Heonki Kirr, Sunghwa Ok, Yongsoon Park, Juhyeong Lee, Sooyeol Chai, Hyeonsu Nam, Heejoo Lee, Tae-Sung Jung, Sang Kyu Lee, Jayoon Goo, Hwang Huh, Woopyo Jeong, Kangwook Jo, Geonu Kim, Yujin Yang, Jangwon Park, Chanhui Jeong, Yujong Noh, Hanna Cho, Wanik Cho, Jinhaeng Lee |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES business.industry Computer science Nand flash memory 020208 electrical & electronic engineering Solid-state Window (computing) 02 engineering and technology 01 natural sciences Non-volatile memory Memory cell 0103 physical sciences 0202 electrical engineering electronic engineering information engineering business Throughput (business) Computer hardware |
| Zdroj: | ISSCC |
| Popis: | Ever since a 3b/cell (TLC) NAND Flash memory became the mainstream in nonvolatile memory market, a new demand for a 4b/cell (QLC) NAND flash memory has been emerging for low-cost applications. However, QLC has inherently much longer page program time than TLC because of 16-state programming within a limited program and erase (PE) window, as well as narrower V th distributions. The longer page-program time, subsequently, degrades sequential write performance. Thus it is not possible to meet the required sequential-write performance in applications such as mobile devices and solid state drives (SSDs). |
| Databáze: | OpenAIRE |
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