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The paper describes a new method for time-to-digital conversion that allows achieving the conversion resolution far below the propagation time of the fastest delay buffer in integrated circuit (IC). The method is a combination of the multi-edge time coding and time digitization in independent coding lines. The implementation of such combination and assessment of its effectiveness are the main aims of this research. The article also describes the main design issues that were solved during the implementation of method in an FPGA device. They include: the generation of a pattern square signal with a certain amount of edges and possibly minimal delays between them, the elimination of bubble errors and reduction of internal interferences in IC. |
