| Popis: |
The coupling noise between adjacent interconnects has become major SI issue, due to higher aspect ratios of interconnects in DSM chips, giving rise to cross talk failures. The Genetic Algorithms (GA) have been applied earlier in different engineering disciplines as potentially good optimization tools and also for various applications in VLSI Design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and cross talk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for cross talk-induced faults between on-chip aggressor and victim and as well as for stuck-at faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns. |
