Enabling technologies for 3D chip stacking

Autor:	Laurent Clavelier, R. Quenouillere, Maxime Rousseau, L. Di Cioccio, Nicolas Sillon, Myriam Assous, P. Gueguen, O. Rozeau, A. Roule, Alain Toffoli, P. Leduc, Antonio Roman, Laurent Vandroux, Barbara Charlet, Paul-Henri Haumesser, D. Bouchu, P. Sixt, Sylvain Maitrejean, M. Heitzmann, J.-P. Nieto, M. Zussy
Rok vydání:	2008
Předmět:	Substrate (building) Materials science business.industry Wafer bonding Spice Stacking Electronic engineering Optoelectronics Three-dimensional integrated circuit Integrated circuit design Direct bonding business Noise (electronics)
Zdroj:	2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
DOI:	10.1109/vtsa.2008.4530806
Popis:	This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV resistance
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::f5f97dc045d99b8d9b0e8bd1bf7b5e97 https://doi.org/10.1109/vtsa.2008.4530806 Zobrazit plný text záznamu