| Popis: |
This letter proposes a robust synchronous wide-range clocked level converter (LC) that converts subthreshold input signals to high I/O voltages for ultra-low power (ULP) SoCs. By biasing the circuit using nMOS leakage current, the design offers robust operation across a wide range of low- and high-supply voltages as well as PVT variations. The design was fabricated in 55-nm CMOS process and shows 60.5-fJ ( $V_{\mathrm{ DDH}}=2.5$ V) switching energy, marking a $2.6\times $ improvement over prior works. |
