| Autor: |
Mehdi Saligane, Jeongsup Lee, David Blaauw, Dennis Sylvester |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
IEEE Solid-State Circuits Letters. 3:130-133 |
| ISSN: |
2573-9603 |
| DOI: |
10.1109/lssc.2020.3007875 |
| Popis: |
This letter proposes a robust synchronous wide-range clocked level converter (LC) that converts subthreshold input signals to high I/O voltages for ultra-low power (ULP) SoCs. By biasing the circuit using nMOS leakage current, the design offers robust operation across a wide range of low- and high-supply voltages as well as PVT variations. The design was fabricated in 55-nm CMOS process and shows 60.5-fJ ( $V_{\mathrm{ DDH}}=2.5$ V) switching energy, marking a $2.6\times $ improvement over prior works. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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