Implementation of a third-generation 1.1-GHz 64-bit microprocessor

Autor:	G.K. Konstadinidis, K. Normoyle, null Samson Wong, S. Bhutani, H. Stuimer, T. Johnson, A. Smith, D.Y. Cheung, F. Romano, null Shifeng Yu, null Sung-Hun Oh, V. Melamed, S. Narayanan, D. Bunsey, null Cong Khieu, K.J. Wu, R. Schmitt, A. Dumlao, M. Sutera, null Jade Chau, K.J. Lin, W.S. Coates
Rok vydání:	2002
Předmět:	Very-large-scale integration Hardware_MEMORYSTRUCTURES UltraSPARC business.industry Computer science Transistor Memory bandwidth Hardware_PERFORMANCEANDRELIABILITY Chip law.invention Microprocessor Read-write memory Hardware_GENERAL law Hardware_INTEGRATEDCIRCUITS System on a chip Cache Electrical and Electronic Engineering business Computer hardware Hardware_LOGICDESIGN
Zdroj:	IEEE Journal of Solid-State Circuits. 37:1461-1469
ISSN:	0018-9200
DOI:	10.1109/jssc.2002.803951
Popis:	This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13-/spl mu/m CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::f5b7fb8bf3a822bbf618554316802a61 https://doi.org/10.1109/jssc.2002.803951 Zobrazit plný text záznamu