| Autor: |
P.O. Sassoulas, Francois Wacquant, J. Todeschini, M. Woo, M. Charpin, Y. Laplanche, N. Revil, J.C. Oberlin, Roland Pantel, B. Hinschberger, O. Belmont, D. Neira, P. Stolk, Franck Arnaud, M. Broekaart, Frederic Boeuf, I. Guilmeau, D. Ceccarelli, Francois Leverd, N. Emonet, Damien Lenoble, Bertrand Borot, G. Imbert, N. Bicais, S. Delmedico, A. Sicard, Nicolas Planes, J. Farkas, Christophe Regnier, V. Vachellerie, J. Uginet, Chittoor Parthasarathy, E. Denis, V. DeJonghe, Pierre Morin, T. Devoivre, H. Brut, R. Palla, Laurent Pain, P. Vannier, F. Salvetti, A. Beverina, C. Perrot |
| Rok vydání: |
2004 |
| Předmět: |
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| Zdroj: |
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407). |
| Popis: |
This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V/sub dd/=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V/sub th/-L/sub d/ and V/sub th/-W/sub d/ profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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