A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range
| Autor: | Jihoon Jeong, Francois Ibrahim Atallah, Keith Bowman, J. Todd Bridges, Daniel Yingling, Brad Appel, Sarthak Raina, David W. Hansquine, Hoan Huu Nguyen, Yesh Kolla |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Physics
020208 electrical & electronic engineering Clock rate Response time 02 engineering and technology Topology 020202 computer hardware & architecture Frequency divider Phase-locked loop Control theory 0202 electrical engineering electronic engineering information engineering Voltage droop Electrical and Electronic Engineering Throughput (business) Energy (signal processing) Voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 51:8-17 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2015.2473655 |
| Popis: | A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage $({\rm V}_{\rm DD})$ droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency $({\rm F}_{\rm CLK})$ adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce ${\rm F}_{\rm CLK}$ in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect ${\rm V}_{\rm DD}$ droops across a wide range of operating conditions. The auto-calibration circuit maximizes the ${\rm V}_{\rm DD}$ -droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% ${\rm V}_{\rm DD}$ droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|