Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

Autor:	Rolf Lagerquist, C. Raibaut, Hugh Mair, J. L. Lachese, L. Bouetel, J. Ciroux, F. Piacibello, F. Ben-Amar, Vinod Menezes, F. Jumel, David B. Scott, J. Rosal, Sudha Thiruvengadam, Philippe Royannez, Norman L. Culp, A.E. Rachidi, S. Gururajarao, Michael Patrick Clinton, J. Vaccani, O. Domerego, M. Ball, Uming U. Ko, Minh Chau, R. Hollingsworth, C. Foumet-Fayard
Rok vydání:	2007
Předmět:	Engineering Hardware_MEMORYSTRUCTURES Power gating business.industry Clock gating Hardware_PERFORMANCEANDRELIABILITY Chip Hardware_GENERAL Embedded system Management system Hardware_INTEGRATEDCIRCUITS Baseband Wireless System on a chip business Hardware_LOGICDESIGN Leakage (electronics)
Zdroj:	2007 IEEE International Conference on Integrated Circuit Design and Technology.
DOI:	10.1109/icicdt.2007.4299538
Popis:	Leakage power management, wireless SoC In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-uA range and overall 1200X leakage reduction including process, circuit and system optimization.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::f481689c333b1ca11827ed7a69e5b15a https://doi.org/10.1109/icicdt.2007.4299538 Zobrazit plný text záznamu