| Autor: |
Keiji Shinohara, Yukihiro Kamide, Kazushi Wada, H. Yamada, Michio Negishi, T. Tsunakawa, T. Yamasaki, T. Ishimaru, M. Yamagishi, Kensuke Harada, T. Iizuku, Satoshi Nakamura, Kazuya Yonemoto |
| Rok vydání: |
1990 |
| Předmět: |
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| Zdroj: |
1990 37th IEEE International Conference on Solid-State Circuits. |
| DOI: |
10.1109/isscc.1990.110201 |
| Popis: |
The image area of the frame FIT (frame-interline-transfer)-CCD (charge-coupled-device) image sensor is 14.0 mm (H)*7.9 mm (V), the effective number of pixels is 1920 (H)*1036 (V) and the unit cell size of a pixel is 7.3 mu m (H)*7.6 mu m (V). These specifications are for the high-definition-television (HDTV) format. The horizontal shift register consists of dual-channel, two-phase CCDs driven by a 37.125-MHz clock pulse. The readout phase of each channel is the same, which allows the reset gate of each channel to be connected together. To adapt to the 74.25-MHz readout frequency, one of the output signals is delayed by 13.47 ns through a sample-hold circuit. To reduce the voltage drop of the vertical shift register (V-CCD) drive pulse along the poly-Si transfer gate, an Al wire is put onto the transfer gate and interconnected to decrease the resistance. This Al wire works also as a photoshield. In addition, another poly-Si layer placed between the Al wire and the transfer gate prevents potential shift by separating the poly-Si contact of the transfer gate/poly-Si layer, from the Al contact of the poly-Si layer/Al wire. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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