Electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards
| Autor: | Michael W. Cresswell, S.C. Everist, J.E. Bonevich, Christine E. Murabito, Loren W. Linholm, L.A. Giannuzzi, P.J. Shea, N.M.P. Guillaume, R.A. Allen |
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| Rok vydání: | 2001 |
| Předmět: |
Fabrication
Materials science business.industry Silicon on insulator Condensed Matter Physics Industrial and Manufacturing Engineering Electronic Optical and Magnetic Materials law.invention Metrology Laser linewidth Surface micromachining Optics law Microscopy Electrical and Electronic Engineering Resistor High-resolution transmission electron microscopy business |
| Zdroj: | IEEE Transactions on Semiconductor Manufacturing. 14:356-364 |
| ISSN: | 0894-6507 |
| DOI: | 10.1109/66.964322 |
| Popis: | Electrical test structures known as cross-bridge resistors have been patterned in [100] epitaxial silicon material that was grown on Bonded and Etched-back Silicon-On-Insulator (BESOI) substrates. The critical dimensions (CDs) of a selection of their reference segments have been measured electrically, by scanning-electron microscopy (SEM), and by lattice-plane counting. The lattice-plane counting is performed on phase-contrast images of the cross sections of the reference segments that are produced by high-resolution transmission-electron microscopy (HRTEM). The reference-segment features were aligned with [110] directions in the BESOI surface material. They were defined by a silicon micromachining process that resulted in their sidewalls being nearly atomically planar and smooth and inclined at 54.737/spl deg/ to the surface [100] plane of the substrate. SEM, HRTEM, and electrical CD (ECD) linewidth measurements have been made on features of various drawn dimensions on the same substrate to investigate the feasibility of a CD traceability path that combines the low cost, robustness, and repeatability of ECD metrology and the absolute measurement of the HRTEM lattice-plane counting technique. Other novel aspects of the [100] silicon-on-insulator (SOI) implementation that are reported here are the ECD test-structure architecture and the making of lattice-plane counts from cross-sectional HRTEM imaging of the reference features. This paper describes the design details and the fabrication of the cross-bridge resistor test structure. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross sections of the cross-bridge resistors' reference segments, as a prelude to making them available for dimensional reference applications. |
| Databáze: | OpenAIRE |
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