| Autor: |
Pierre-André Farine, Steve Tanner, Yazhou Zhao, Florian Gruet, Luc Schneller, Christoph Affolderbach, Gaetano Mileti |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 Joint European Frequency and Time Forum & International Frequency Control Symposium (EFTF/IFC). |
| Popis: |
In this paper, we present the characterization results of an optimized 4.6 GHz frequency synthesizer ASIC targeted for miniature atomic clock applications. Fabricated into a 130 nm RF CMOS process, the circuit occupies an active area of 2 mm2 and consumes 15 mW of power. The measured phase noise is about -85 dBc/Hz in the range of 2 kHz to 100 kHz frequency offset from the carrier. The circuit was used as RF synthesizer in an experimental cesium atomic clock setup. The obtained clock stability of 5×10-11 at τ = 1 second corresponds to the stability obtained with a laboratory synthesizer on the same setup, and is limited by the signal-to-noise ratio of the detected CPT signal. The theoretical stability limit due to the ASIC phase noise is 2×10-11 τ -1/2, which is not limiting the measured clock stability. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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