| Autor: |
Chi-Weon Yoon, Hoi-Jun Yoo, Kangmin Lee, Ramchan Woo, Jeonghoon Kook, Yong-Ha Park, Se-Joong Lee |
| Rok vydání: |
2002 |
| Předmět: |
|
| Zdroj: |
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185). |
| DOI: |
10.1109/vlsic.2001.934206 |
| Popis: |
An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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