High Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000
| Autor: | Nattha Jindapetch, Surachate Chumpol, Kiattisak Sengchuai, Apidet Booranawong, Pakpoom Hoyingcharoen, Panadda Solod, Masami Ikura |
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| Rok vydání: | 2021 |
| Předmět: |
Computer science
business.industry 010401 analytical chemistry General Engineering 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences 0104 chemical sciences Embedded system High-level synthesis Lane detection 0210 nano-technology business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION |
| Zdroj: | Pertanika Journal of Science and Technology. 29 |
| ISSN: | 2231-8526 |
| DOI: | 10.47836/pjst.29.2.01 |
| Popis: | In this work, we proposed High-Level Synthesis (HLS) optimization processes to improve the speed and the resource usage of complex algorithms, especially nested-loop. The proposed HLS optimization processes are divided into four steps: array sizing is performed to decrease the resource usage on Programmable Logic (PL) part, loop analysis is performed to determine which loop must be loop unrolling or loop pipelining, array partitioning is performed to resolve the bottleneck of loop unrolling and loop pipelining, and HLS interface is performed to select the best block level and port level interface for array argument of RTL design. A case study road lane detection was analyzed and applied with suitable optimization techniques to implement on the Xilinx Zynq-7000 family (Zybo ZC7010-1) which was a low-cost FPGA. From the experimental results, our proposed method reaches 6.66 times faster than the primitive method at clock frequency 100 MHz or about 6 FPS. Although the proposed methods cannot reach the standard real-time (25 FPS), they can instruct HLS developers for speed increasing and resource decreasing on an FPGA. |
| Databáze: | OpenAIRE |
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