Low-swing self-timed regenerators for high-speed and low-power on-chip global interconnects
| Autor: | Hossein Rezaei, Soodeh Aghli Moghaddam |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering 02 engineering and technology Propagation delay Swing 020202 computer hardware & architecture Power (physics) Reduction (complexity) Noise margin CMOS Regenerative heat exchanger 0202 electrical engineering electronic engineering information engineering Electronic engineering business Repeater insertion |
| Zdroj: | 2016 24th Iranian Conference on Electrical Engineering (ICEE). |
| DOI: | 10.1109/iraniancee.2016.7585515 |
| Popis: | In this paper, a novel mixed design of low-swing self-timed regenerator (LS-STR) is presented. The new design reduces the energy-delay product (EDP) and eliminates a fabrication constraint. Thus, the LS-STR is suitable for long global on-chip interconnects. The proposed scheme is simulated using CMOS 90-nm technology at 1.0 V power supply rail, for signal transmission along a 10-mm length line. The simulation results for different wire widths reveal that the propagation delay is reduced by 39.1% for iso-power mode when compared with the delay of optimal repeater insertion. Also, up to 23.2% power reduction is achieved in the iso-delay mode. A key advantage of the proposed LS-STR is that it employs neither multiple-threshold process technology nor an extra and different power supply rail, while the noise margin remains in an acceptable level. |
| Databáze: | OpenAIRE |
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