VHDL Semantics for Behavioral Test Generation
| Autor: | Chang H. Cho, James R. Armstrong |
|---|---|
| Rok vydání: | 1991 |
| Předmět: |
Statement (computer science)
Computer science Semantics (computer science) Programming language media_common.quotation_subject Process (computing) Resolution (logic) computer.software_genre Asynchronous communication VHDL Sensitivity (control systems) Function (engineering) computer media_common computer.programming_language |
| DOI: | 10.1016/b978-0-444-89208-9.50030-2 |
| Popis: | In this paper, we discuss how the VHDL semantics which represent the concepts of event-driven simulation and bus resolution function affect the test generation algorithm, and present methods of generating realistic tests without being affected by the VHDL semantics. A formal representation of the VHDL process statement is described and the concept of event-driven simulation and its impact on test generation are discussed using the formal representation. The new test generation method generates realistic tests by ignoring the sensitivity list of a process statement and identifying the type of the behavior described by the statements inside the process statement (two types of behavior - synchronous and asynchronous, are defined.). A systematic way of converting a VHDL model to one suitable for checking the validity of the generated tests is presented. A method of further compacting the generated tests is also presented. Finally, an approach to generating tests in the presence of different types of bus resolution functions is discussed. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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