Optimization of gate stack parameters towards 3D-SONOS application

Autor: G. Van den bosch, Baojun Tang, Ingrid Debusschere, Laurent Breuil, Antonio Arreghini, Gouri Sankar Kar, L. Date, J. Van Houdt, A. Cacciato
Rok vydání: 2011
Předmět:
Zdroj: Microelectronic Engineering. 88:1164-1167
ISSN: 0167-9317
DOI: 10.1016/j.mee.2011.03.140
Popis: A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation.
Databáze: OpenAIRE