| Autor: |
Hirohito Higashi, Atsushi Matsuda, Masahiro Kudo, Kazuhiro Terashima, Shigeaki Kawai, Tomokazu Higuchi, Yutaka Ide, Futoshi Terasawa, Naoaki Naka, Hideki Kano, Noriaki Shirai, Tomoyuki Arai, Hiroki Miyaoka |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
A-SSCC |
| DOI: |
10.1109/asscc.2015.7387468 |
| Popis: |
A low-power and area optimized 28-nm CMOS 28-Gb/s transceiver is presented. The transceiver comprised with one PLL shared with 4 transceiver lanes. To meet the CEI-28G-VSR and CAUI4 (chip-to-module) standards, a 1-tap DFE is employed for the receiver. The power reduction is realized by employing 1-tap loop unrolled DFE circuits with domino logic and dynamic latches, and eliminating FFE. The transceiver occupies 2.31 mm2 and consumes 505 mW (4.5 pJ/bit). |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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