High performance memory mode control for HDTV decoders
| Autor: | Seong-II Park, Yongseok Yi, In-Cheol Park |
|---|---|
| Rok vydání: | 2003 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Flat memory model Computer science business.industry Cache-only memory architecture Uniform memory access Registered memory Semiconductor memory CAS latency Extended memory Non-uniform memory access Memory address Embedded system Memory architecture Media Technology Interleaved memory Computing with Memory Electrical and Electronic Engineering Memory refresh business Conventional memory |
| Zdroj: | IEEE Transactions on Consumer Electronics. 49:1348-1353 |
| ISSN: | 0098-3063 |
| DOI: | 10.1109/tce.2003.1261239 |
| Popis: | To increase the bandwidth of synchronous memories that are widely adopted for HDTV decoder systems, a predictive mode control scheme is proposed in this paper. Memory latency and energy consumption can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory code. In a HDTV decoder system, experimental results show that the proposed scheme reduces the memory latency and the energy consumption by 18.8% and 23.3%, respectively, over the conventional scheme that always keeps the memory in idle state. Hardware architecture and its VLSI implementation are also presented. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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