High efficiency synchronous DRAM controller for H.264 HDTV encoder
| Autor: | Sun Jingnan, Hu Hongqi, Xu Jiadong |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
business.industry Computer science Memory bus Memory bandwidth Data_CODINGANDINFORMATIONTHEORY Memory controller CAS latency Memory management Control theory Embedded system Bandwidth (computing) ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS business Encoder Computer hardware Dram |
| Zdroj: | 2009 4th IEEE Conference on Industrial Electronics and Applications. |
| DOI: | 10.1109/iciea.2009.5138526 |
| Popis: | This paper addresses a high efficiency memory controller of Synchronous DRAM to improve memory bandwidth in H.264/AVC HDTV encoder. The feature of SDRAM and memory access patterns of H.264/AVC encoder are analyzed for suitable controller architecture designing. Based on page breaks analysis of memory access patterns, a new data arrangement in SDRAM has been used to improve bus efficiency in H.264/AVC HDTV encoder by reducing the overhead cycle of page-activation. In addition, in order to reduce the bandwidth requirement, a well-arranged frame buffer is used in proposed SDRAM controller. Experiment results show that the proposed architecture has improved 40% performance of SDRAM bus efficiency. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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