Localization of Gate Bias Induced Threshold Voltage Degradation in a-Si:H TFTs
| Autor: | Sameer M. Venugopal, Lawrence T. Clark, David R. Allee, Edward J. Bawolek, R. Shringarpure |
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| Rok vydání: | 2008 |
| Předmět: |
Amorphous silicon
Materials science Silicon business.industry Electrical engineering chemistry.chemical_element Biasing Drain-induced barrier lowering Electronic Optical and Magnetic Materials Threshold voltage Amorphous solid Stress (mechanics) chemistry.chemical_compound chemistry Thin-film transistor Optoelectronics Electrical and Electronic Engineering business |
| Zdroj: | IEEE Electron Device Letters. 29:93-95 |
| ISSN: | 1558-0563 0741-3106 |
| DOI: | 10.1109/led.2007.911609 |
| Popis: | This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage(Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived. |
| Databáze: | OpenAIRE |
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