| Autor: |
E. Leobandung, E. Barth, M. Sherony, S.-H. Lo, R. Schulz, W. Chu, M. Khare, D. Sadana, D. Schepis, R. Boiam, I. Sleight, F. White, F. Assaderaghi, D. Moy, G. Biery, R. Goldblan, T.-C. Chen, B. Davari, G. Shahidi |
| Rok vydání: |
2003 |
| Předmět: |
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| Zdroj: |
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318). |
| Popis: |
A 0.18 /spl mu/m SOI CMOS technology is presented. Key features in this technology are: more aggressive gate lithography (equivalent to 0.15 /spl mu/m half pitch generation) and devices than previously reported 0.18 /spl mu/m CMOS technology, low dose SIMOX SOI substrate, dual gate oxide, low /spl epsi/ BEOL insulator, and 7 layer copper metalization. Inverter delay of less than 6.5 ps has been achieved with this technology. A POWER4/sup TM/ test chip was built using the 0.18 /spl mu/m SOI technology and has demonstrated performance above 1 GHz. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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