A 9-nW on-chip constant subthreshold CMOS transconductance bias with fine-tuning
| Autor: | Theodore W. Berger, Uldric Antao, John Choma Ming Hsieh |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Materials science
Negative-bias temperature instability Subthreshold conduction business.industry Transconductance 020208 electrical & electronic engineering Transistor Electrical engineering 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Hybrid-pi model law.invention Threshold voltage law Operational transconductance amplifier Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering business NMOS logic Hardware_LOGICDESIGN |
| Zdroj: | ISCAS |
| DOI: | 10.1109/iscas.2017.8050291 |
| Popis: | A novel 9 nW process, voltage, and temperature invariant subthreshold transconductance bias circuit is designed using a 150 nm CMOS process with BSIM3.V3 models. The circuit uses no external components or strong inversion transistors, drastically reducing complexity and lowering power compared with prior work. The proposed method extracts the specific current of a transistor and is then passed through a squaring circuit to deliver a constant transconductance bias over temperature in subthreshold region. We also propose a unique fine-tuning block that improves the robustness of the transconductance using the difference in the mobility temperature exponent, m, of electrons of differently-sized NMOS transistors. Simulations show that the circuit outperforms prior work with the least variation in subthreshold transconductance of +0.63% over −40 °C to 125 °C. |
| Databáze: | OpenAIRE |
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