ASIC Synthesis and Design Constraints
| Autor: | Vaibbhav Taraate |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
business.industry
Computer science Latency (audio) computer.software_genre Power (physics) Clock network Logic synthesis Application-specific integrated circuit Scripting language Embedded system Physical synthesis business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer AND gate Hardware_LOGICDESIGN |
| Zdroj: | Logic Synthesis and SOC Prototyping ISBN: 9789811513138 |
| DOI: | 10.1007/978-981-15-1314-5_7 |
| Popis: | The chapter discusses the ASIC synthesis and frequently used Synopsys DC commands and their role during ASIC synthesis. Even the chapter discusses about the design partitioning, synthesis guidelines, and design constraints. The DC commands used during the synthesis and their role are described for better understanding of synthesis scripts or to create synthesis scripts for the required constratints. The chapter is useful to understand the area, speed constraints, and logic synthesis using Synopsys DC. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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