Comprehensive optimization of scan chain timing during late-stage IC implementation
| Autor: | Jiajia Li, Kun Young Chung, Andrew B. Kahng |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 0211 other engineering and technologies Scan chain Skew Static timing analysis 02 engineering and technology Clock skew 020202 computer hardware & architecture Logic gate 0202 electrical engineering electronic engineering information engineering Routing (electronic design automation) business Voltage drop Computer hardware 021106 design practice & management Degradation (telecommunications) |
| Zdroj: | DAC |
| Popis: | Scan chain timing is increasingly critical to test time and product cost. However, hold buffer insertions (e.g., due to large clock skew) limit scan timing improvement. Dynamic voltage drop (DVD) during scan shift further degrades scan shift timing, inducing "false failures" in silicon. Hence, new optimizations are needed in late stages of implementation when accurate (skew, DVD) information is available. We propose skew-aware scan ordering to minimize hold buffers, and DVD-aware gating insertion to improve scan shift timing slacks. Our optimizations at the post-CTS and post-routing stages reduce hold buffers by up to 82%, and DVD-induced timing degradation by up to 58%, with negligible area and power overheads. |
| Databáze: | OpenAIRE |
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