Integrated flow for reverse engineering of nanoscale technologies
| Autor: | P. Egger, H. Gieser, Helmut Graeb, Oliver Kellermann, Anja Dübotzky, Aayush Singla, Michael Werner, Niklas Unverricht, Bernhard Lippmann, Martin Rasche |
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| Rok vydání: | 2019 |
| Předmět: |
Reverse engineering
business.industry Computer science Process (computing) Image processing 02 engineering and technology Integrated circuit 021001 nanoscience & nanotechnology Encryption computer.software_genre Circuit extraction 020202 computer hardware & architecture law.invention Flow (mathematics) law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Figure of merit 0210 nano-technology business computer Computer hardware |
| Zdroj: | ASP-DAC |
| DOI: | 10.1145/3287624.3288738 |
| Popis: | In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS will be compared quantitatively as a figure of merit (FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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