On-Chip Property Verification Using Assertion Processors

Autor:	Jose Augusto M. Nacif, Harry Foster, Edjard Mota, A.O. Fernandes, Flavio M. de Paula, Claudionor Coelho, Márcia Roberta Falcão Mota
Rok vydání:	2006
Předmět:	Emulation Property (programming) Computer science business.industry media_common.quotation_subject Assertion Chip Debugging Computer architecture TheoryofComputation_LOGICSANDMEANINGSOFPROGRAMS Embedded system Observability business media_common
Zdroj:	IFIP International Federation for Information Processing ISBN: 9780387334028 VLSI-SoC (Selected Papers)
DOI:	10.1007/0-387-33403-3_7
Popis:	White-box verification is a technique that reduces observability problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using assertion checkers to ensure the correct behavior of a design. With chip gate counts growing exponentially, today’s verification techniques, such as white-box, can not always ensure a bug free design. This paper proposes an assertion processor to be used with synthesized assertion checkers in released products to enable intelligent debugging of deployed designs. Extending white-box verification techniques to deployed products helps locate errors that were not found during simulation / emulation phases. We present results of the insertion of assertion checkers and an assertion processor in an 8-Bit processor and a communication core.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::eff9a878b9bdd254d3898d7f3b00f796 https://doi.org/10.1007/0-387-33403-3_7 Zobrazit plný text záznamu