PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers

Autor:	Jin Zhang, Fei Lyu, Yu Wang, Yuanyong Luo, Zhelong Mao
Rok vydání:	2021
Předmět:	Piecewise linear function Significand Floating point Logarithm Hardware and Architecture Computer science Approximation error Piecewise Approximation algorithm Electrical and Electronic Engineering CORDIC Algorithm Software
Zdroj:	IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:1470-1474
ISSN:	1557-9999 1063-8210
Popis:	In this brief, we propose a logarithmic converter for floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method is applicable to any customized floating-point format with a mantissa length of 16–23 bits and a maximum absolute error (MAE) larger than 10−6. The logarithmic function is automatically segmented into several maximal subsections by a software-based segmentation scheme with the restriction of a predefined MAE and a fractional word length for the computing units. Then, we make a tradeoff between the piecewise number and the fractional word length. Based on the results of the segmentor, our design is coded in the Verilog hardware description language. The synthesized results show that our design consumes less area, time, and power without compromising accuracy compared to existing techniques based on the COordinate Rotation Digital Computer (CORDIC) and PWL methods.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::eff85a3d86035594845d3cdca8a282c2 https://doi.org/10.1109/tvlsi.2021.3081572 Zobrazit plný text záznamu