| Autor: |
I. Sen Gupta, Sudip Roy, Ajit Pal |
| Rok vydání: |
2008 |
| Předmět: |
|
| Zdroj: |
TENCON 2008 - 2008 IEEE Region 10 Conference. |
| DOI: |
10.1109/tencon.2008.4766747 |
| Popis: |
As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as well as the test engineers. Test vector reordering for dynamic power minimization during combinational circuit testing is a sub-problem of the general goal of low power testing. In this paper we have proposed an AI-based approach to order the test vectors in an optimal manner to minimize switching activity during testing. Empirically, the proposed algorithm yields on an average of about 22% reduction in switching activity over that given by a standard ATPG tool Synopsis TetraMax, which is also more than the reduction after applying existing Chained Lin-Kernighan heuristic. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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