FPGA-based 3D median filtering using word-parallel systolic arrays

Autor:	Carlos R. Castro-Pareja, Jogikal M. Jagadeesh, Raj Shekhar, Sharmila Venugopal
Rok vydání:	2004
Předmět:	Computer science business.industry Noise reduction Clock rate Image processing Systolic array Filter (signal processing) Kernel (image processing) Median filter Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array business Computer hardware
Zdroj:	ISCAS (3)
DOI:	10.1109/iscas.2004.1328707
Popis:	A 3D median filter architecture suitable for FPGA implementation is presented. The architecture consists of an ordered semi-systolic array of size equal to the filter window size. The hardware requirements of the architecture are significantly lower than those of previously reported systolic array architectures, making it desirable for the implementation of filters with large kernel sizes. An implementation of a 3/spl times/3/spl times/3/spl times/ filter in an Altera EP1C3T100C6 FPGA achieved a clock rate in excess of 100 MHz, being able to process a 128/spl times/128/spl times/128 image in 0.2 seconds. An implementation of a 3/spl times/3 2D filter achieved a clock rate in excess of 130 MHz.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ef8c52dcdc7b28dfaa67c67ff216d121 https://doi.org/10.1109/iscas.2004.1328707 Zobrazit plný text záznamu