Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion
| Autor: | Soner Yesil, Cansu Sen, Ali Ozgur Yilmaz |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
SIMPLE (military communications protocol)
business.industry Time delay neural network Computer science 020208 electrical & electronic engineering Activation function 020206 networking & telecommunications 02 engineering and technology Adaptive hardware Predistortion 0202 electrical engineering electronic engineering information engineering Device under test business Field-programmable gate array Throughput (business) Computer hardware |
| Zdroj: | ICECS |
| Popis: | This paper presents an FPGA implementation of the Real Valued Time Delay Neural Network (RVTDNN) based digital predistortion with a very low resource utilization and high throughput. The implementation exploits efficient utilization of FPGA primitives and approximation of activation functions that can be realized with simple logic operations. The proposed modifications and constraints on the algorithms have been decided and verified based on a closed-loop adaptive hardware setup including RFHIC RWP03040-1H PA as the unit under test together with injected RF impairments. Over 20dB of in-band performance gain has been reported with a (4,8,2) RVTDNN configuration utilizing only 52 DSP48 blocks, 224 LUTs and 120 FFs. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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