Hierarchical physical design methodology for multi-million gate chips

Autor:	Wei-Jin Dai
Rok vydání:	2001
Předmět:	Computer architecture Computer science business.industry Embedded system Hardware_INTEGRATEDCIRCUITS Hardware_PERFORMANCEANDRELIABILITY Physical design business Design methods Floorplan Hierarchical design
Zdroj:	ISPD
DOI:	10.1145/369691.369766
Popis:	In this paper, a design methodology for the implementation of multi-million gate system-on-chip designs is described.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::eefe6a9ef560d5c372e8a8232d79b51e https://doi.org/10.1145/369691.369766 Zobrazit plný text záznamu