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This paper describes the concurrent error-detection methods employed in the ERC32, a 32-bit processing core for embedded space flight applications. The processor core consists of three devices; an integer unit, a floating point unit and a memory controller. All three devices are provided with internal concurrent error-detection, mainly to detect transient errors. Over 98% of all latched errors are detected. Depending on the error location, errors can be removed by instruction retry or by software intervention without loss of context. A program flow control mechanism is provided to detect execution anomalies due to undetected errors. To further increase the error-detection coverage, each device can be operated in master/checker mode. > |
